The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), which may be realized as metal oxide semiconductor field effect transistors (MOSFETs or MOS transistors). A MOS transistor may be realized as a p-type device (i.e., a PMOS transistor) or an n-type device (i.e., an NMOS transistor). Moreover, a semiconductor device can include both PMOS and NMOS transistors, and such a device is commonly referred to as a complementary MOS or CMOS device. A MOS transistor includes a gate electrode as a control electrode that is formed over a semiconductor substrate, and spaced-apart source and drain regions formed within the semiconductor substrate and between which a current can flow. The source and drain regions are typically accessed via respective silicide conductive contacts formed on the source and drain regions. Bias voltages applied to the gate electrode, the source contact, and the drain contact control the flow of current through a channel in the semiconductor substrate between the source and drain regions beneath the gate electrode. Conductive metal interconnects (plugs) formed in an insulating layer are typically used to deliver bias voltages to the gate, source, and drain contacts.
FIG. 1 is a simplified diagram of a CMOS transistor device structure 100 that has been fabricated using conventional techniques. The upper portion of FIG. 1 (FIG. 1A) represents a top view of device structure 100, and the lower portion of FIG. 1 (FIG. 1B) represents a cross section of device structure 100 as viewed from line 1B-1B in the upper portion of FIG. 1. Device structure 100 includes an n-type active region 102 of semiconductor material, a p-type active region 104 of semiconductor material, shallow trench isolation (STI) 106 surrounding and separating n-type region 102 and p-type region 104, and a gate structure 108 overlying n-type region 102, p-type region 104, and STI 106. Device structure 100 is formed on a silicon-on-insulator (SOI) substrate having a physical support substrate 110 and an insulating material 112 (typically a buried oxide) on support substrate 110. Gate structure 108 includes a gate insulator layer 114, which is formed from a dielectric material having a relatively high dielectric constant (i.e., a high-k material). Gate structure 108 also includes a gate metal layer 116 overlying gate insulator layer 114, and a layer of polycrystalline silicon 118 overlying gate metal layer 116.
FIG. 2 is a detailed view of a region 120 of device structure 100 (this region 120 is surrounded by the dashed circle in FIG. 1). FIG. 2 shows a divot 122 that can be formed as a result of one or more process steps that lead to the formation of device structure 100. Gate insulation layer 114, gate metal layer 116, and polycrystalline silicon 118 generally follow the contour of divot 122 as they are formed. The arrows in FIG. 2 represent the liberation of oxygen from STI 106 into gate insulator layer 114. The diffusion of oxygen through the high-k gate insulator layer 114 and over p-type region 104 causes the “width effect,” which can degrade device performance. Although not shown in FIG. 2, the oxygen also diffuses in over the adjacent n-type region, which would be located to the right of the portion of STI 106 shown in FIG. 2. Notably, devices with shorter channel region lengths are more susceptible to the width effect.
The width effect can be reduced using a number of known techniques. One known approach for reducing the width effect adds silicon to the high-k material. However, this adds control issues to dielectric deposition, and adversely impacts scaling. Another known approach for reducing the width effect employs nitridation of the high-k material. However, excess nitridation degrades device performance and can adversely affect the threshold voltage of the device. Yet another approach utilizes oxygen scavenging metals to create the metal gate layer. Unfortunately, oxygen scavenging metals have inherent control issues, which lead to excess variability in the process. The width effect can also be addressed by attempting to minimize the amount of overlap between the underlying STI material and the high-k gate material. Such techniques require additional masking layers, and such techniques might violate existing controls and rules mandated by the particular manufacturing process node. One additional approach encapsulates the STI material with a nitride diffusion barrier prior to the deposition of the high-k material. This approach is unproven, and it leads to significant process complexity for the isolation module and variability to subsequent process modules.